cpu-cache
Line size of L1 and L2 caches
Cache-Lines size is (typically) 64 bytes. Moreover, take a look at this very interesting article about processors caches: Gallery of Processor Cache Effects You will find the following chapters: Memory accesses and performance Impact of cache lines L1 and L2 cache sizes Instruction-level parallelism Cache associativity False cache line sharing Hardware complexities
Which ordering of nested loops for iterating over a 2D array is more efficient [duplicate]
The first method is slightly better, as the cells being assigned to lays next to each other. First method: [ ][ ][ ][ ][ ] …. ^1st assignment ^2nd assignment [ ][ ][ ][ ][ ] …. ^101st assignment Second method: [ ][ ][ ][ ][ ] …. ^1st assignment ^101st assignment [ ][ ][ … Read more
Understanding std::hardware_destructive_interference_size and std::hardware_constructive_interference_size
The intent of these constants is indeed to get the cache-line size. The best place to read about the rationale for them is in the proposal itself: http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0154r1.html I’ll quote a snippet of the rationale here for ease-of-reading: […] the granularity of memory that does not interfere (to the first-order) [is] commonly referred to as … Read more