x86 – Make Me Engineer

How can I mitigate the impact of the Intel jcc erratum on gcc?

By compiler: GCC: -Wa,-mbranches-within-32B-boundaries clang (10+): -mbranches-within-32B-boundaries compiler option directly, not -Wa. MSVC: /QIntel-jcc-erratum See Intel JCC Erratum – what is the effect of prefixes used for mitigation? ICC: TODO, look for docs. The GNU toolchain does mitigation in the assembler, with as -mbranches-within-32B-boundaries, which enables (GAS manual: x86 options): -malign-branch-boundary=32 (care about 32-byte boundaries). … Read more

How to write hello world in assembly under Windows?

This example shows how to go directly to the Windows API and not link in the C Standard Library. global _main extern _GetStdHandle@4 extern _WriteFile@20 extern _ExitProcess@4 section .text _main: ; DWORD bytes; mov ebp, esp sub esp, 4 ; hStdOut = GetstdHandle( STD_OUTPUT_HANDLE) push -11 call _GetStdHandle@4 mov ebx, eax ; WriteFile( hstdOut, message, … Read more

Why are x86 registers named the way they are?

Something i found * EAX – Accumulator Register * EBX – Base Register * ECX – Counter Register * EDX – Data Register * ESI – Source Index * EDI – Destination Index * EBP – Base Pointer * ESP – Stack Pointer

What is the 0x10 in the “leal 0x10(%ebx), %eax” x86 assembly instruction?

leal, or lea full name is “Load effective address” and it does exactly this: It does an address calculation. In your example the address calculation is very simple, because it just adds a offset to ebx and stores the result in eax: eax = ebx + 0x10 lea can do a lot more. It can … Read more

Alignment requirements for atomic x86 instructions vs. MS’s InterlockedCompareExchange documentation?

x86 does not require alignment for a lock cmpxchg instruction to be atomic. However, alignment is necessary for good performance. This should be no surprise, backward compatibility means that software written with a manual from 14 years ago will still run on today’s processors. Modern CPUs even have a performance counter specifically for split-lock detection … Read more

Boolean values as 8 bit in compilers. Are operations on them inefficient?

TL:DR: current compilers still have bool missed-optimizations when doing stuff like (a&&b) ? x : y. But the reason why is not that they don’t assume 0/1, they just suck at this. Many uses of bool are for locals, or inline functions, so booleanizing to a 0 / 1 can optimize away and branch (or … Read more

What does the dollar sign ($) mean in x86 assembly when calculating string lengths like “$ – label”? [duplicate]

In this case, the $ means the current address according to the assembler. $ – msg is the current address of the assembler minus the address of msg, which would be the length of the string.

Do current x86 architectures support non-temporal loads (from “normal” memory)?

To answer specifically the headline question: Yes, recent1 mainstream Intel CPUs support non-temporal loads on normal 2 memory – but only “indirectly” via non-temporal prefetch instructions, rather than directly using non-temporal load instructions like movntdqa. This is in contrast to non-temporal stores where you can just use the corresponding non-temporal store instructions3 directly. The basic … Read more

Does it make any sense to use the LFENCE instruction on x86/x86_64 processors?

Bottom line (TL;DR): LFENCE alone indeed seems useless for memory ordering, however it does not make SFENCE a substitute for MFENCE. The “arithmetic” logic in the question is not applicable. Here is an excerpt from Intel’s Software Developers Manual, volume 3, section 8.2.2 (the edition 325384-052US of September 2014), the same that I used in … Read more

Why is x86 little endian?

Largely, for the same reason you start at the least significant digit (the right end) when you add—because carries propagate toward the more significant digits. Putting the least significant byte first allows the processor to get started on the add after having read only the first byte of an offset. After you’ve done enough assembly … Read more

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