A trap is an exception in a user process. It’s caused by division by zero or invalid memory access. It’s also the usual way to invoke a kernel routine (a system call) because those run with a higher priority than user code. Handling is synchronous (so the user code is suspended and continues afterwards). In … Read more
LBA Disk Access Availability Not all BIOSes support the extended disk read and write functions (although on modern hardware they almost all likely will). Not all BIOSes support extended disk reads of floppies via Int 13h/AH=42h. This is true of BOCHS as well. You can test whether extended disk functions are available on a drive … Read more
Being consistent is the most important thing; If I’m working on existing code that already has LSE-first comments or variable names, I match that. Given the choice, I prefer MSE-first notation in comments, especially when designing something with shuffles or especially packing/unpacking to different element sizes. Intel uses MSE-first not only in their diagrams in … Read more
Currently no implementation of x86 (or any other ISA, as far as I know) supports optimizing silent stores. There has been academic research on this and there is even a patent on “eliminating silent store invalidation propagation in shared memory cache coherency protocols”. (Googling ‘”silent store” cache’ if you are interested in more.) For x86, … Read more
related: https://scicomp.stackexchange.com/questions/35187/is-half-precision-supported-by-modern-architecture – has some info about BFloat16 in Cooper Lake and Sapphire Rapids, and some non-Intel info. Sapphire Rapids will have both BF16 and FP16, with FP16 using the same IEEE754 binary16 format as F16C conversion instructions, not brain-float. And AVX512-FP16 has support for most math operations, unlike BF16 which just has conversion to/from … Read more
Do read along with the Intel optimization manual, current download location is here. When stale (they move stuff around all the time) then search the Intel site for “Architectures optimization manual”. Keep in mind the info there is fairly generic, they disclose only as much as needed to allow writing efficient code. Branch prediction implementation … Read more
x86 can be a broad term that covers all CPUs that are backwards-compatible with 8086, and all extensions to the architecture including x86-64. Note that IA-64 is not x86 at all, it’s Itanium (a 64-bit VLIW architecture with explicit speculation / parallelism). It was also designed by Intel, but is totally unrelated to x86 in … Read more
AMD processor in the early-gigahertz era had a 40 cycle penalty every time you called a function Huh.. so large.. There is an “Indirect branch prediction” method, which helps to predict virtual function jump, IF there was the same indirect jump some time ago. There is still a penalty for first and mispredicted virt. function … Read more
You can abuse PSADBW to calculate horizontal sums of bytes without overflow. For example: pxor xmm0, xmm0 psadbw xmm0, [a + 0] ; sum in 2x 64-bit chunks pxor xmm1, xmm1 psadbw xmm1, [a + 16] paddw xmm0, xmm1 ; accumulate vertically pshufd xmm1, xmm0, 2 ; bring down the high half paddw xmm0, xmm1 … Read more
Hans and DarkDust answer covered i386/i686 and amd64/x86_64, so there’s no sense in revisiting them. This answer will focus on X32, and provide some info learned after a X32 port. x32 is an ABI for amd64/x86_64 CPUs using 32-bit integers, longs and pointers. The idea is to combine the smaller memory and cache footprint from … Read more