I suggest that you download the full software developer’s manual. The documentation is available in separate volumes, but that link gives you all seven volumes in a single massive PDF, which makes it easier to search for things. The answer is in section 3.3.7.1. The first line of that section states In 64-bit mode, an … Read more
As noted below by @thakis, newer versions of Clang (3.5+) accept the -masm=intel argument. For older versions, this should get clang to emit assembly code with Intel syntax: clang++ -S -mllvm –x86-asm-syntax=intel test.cpp You can use -mllvm <arg> to pass in llvm options from the clang command line. Sadly this option doesn’t appear to be … Read more
That’s right, modern x86 CPUs (especially Intel) have very high performance multipliers. imul r, r/m and imul r, r/m, imm are both 3 cycle latency, one per 1c throughput on Intel SnB-family and AMD Ryzen, even for 64bit operand size. On AMD Bulldozer-family, it’s 4c or 6c latency, and one per 2c or one per … Read more
In a multiprocessor system or a multicore processor (Intel Quad Core, Core two Duo etc..) does each cpu core/processor have its own cache memory (data and program cache)? Yes. It varies by the exact chip model, but the most common design is for each CPU core to have its own private L1 data and instruction … Read more
Just imagine, how the processor would execute a typical spin-wait loop: 1 Spin_Lock: 2 CMP lockvar, 0 ; Check if lock is free 3 JE Get_Lock 4 JMP Spin_Lock 5 Get_Lock: After a few iterations the branch predictor will predict that the conditional branch (3) will never be taken and the pipeline will fill with … Read more
It is not really a full answer, but still evidence that the penalty is visible. MSVC 2022 benchmark, compiler with /std:c++latest. #include <chrono> #include <iostream> struct alignas(16) S { char* a; int* b; }; extern “C” void init_fused_copy_unfused(int n, S & s2, S & s1); extern “C” void init_fused_copy_fused(int n, S & s2, S & … Read more
Make sure you don’t have any virtual machines running. In my case, I had genymotion running which was causing this error.
AMD has always in their manual described their implementation of LFENCE as a load serializing instruction Acts as a barrier to force strong memory ordering (serialization) between load instructions preceding the LFENCE and load instructions that follow the LFENCE. The original use case for LFENCE was ordering WC memory type loads. However, after the speculative … Read more
There is no very good way to get accurate and predictable timing from fixed counts for delay loops on a modern x86 PC, especially in user-space under a non-realtime OS like Linux. (But you could spin on rdtsc for very short delays; see below). You can use a simple delay-loop if you need to sleep … Read more
By compiler: GCC: -Wa,-mbranches-within-32B-boundaries clang (10+): -mbranches-within-32B-boundaries compiler option directly, not -Wa. MSVC: /QIntel-jcc-erratum See Intel JCC Erratum – what is the effect of prefixes used for mitigation? ICC: TODO, look for docs. The GNU toolchain does mitigation in the assembler, with as -mbranches-within-32B-boundaries, which enables (GAS manual: x86 options): -malign-branch-boundary=32 (care about 32-byte boundaries). … Read more