x86 has no way to do a store that bypasses or writes through L1D/L2 but not L3. There are NT stores which bypass all cache. Anything that forces a write-back to L3 also forces write-back all the way to memory. (e.g. a clwb instruction). Those are designed for non-volatile RAM use cases, or for non-coherent … Read more
TL:DR: intptr_t might be best in some cases because the signed-overflow boundary is in the middle of the “non-canonical hole”. Treating a value as negative instead of huge may be better if wrapping from zero to 0xFF…FF or vice versa is possible, but pointer+size for any valid size can’t wrap a value from INT64_MAX to … Read more
LBA Disk Access Availability Not all BIOSes support the extended disk read and write functions (although on modern hardware they almost all likely will). Not all BIOSes support extended disk reads of floppies via Int 13h/AH=42h. This is true of BOCHS as well. You can test whether extended disk functions are available on a drive … Read more
Being consistent is the most important thing; If I’m working on existing code that already has LSE-first comments or variable names, I match that. Given the choice, I prefer MSE-first notation in comments, especially when designing something with shuffles or especially packing/unpacking to different element sizes. Intel uses MSE-first not only in their diagrams in … Read more
That assembly language is MASM, not NASM. For starters, NASM segments are defined differently. Instead of Code segment word public ‘CODE’ we write .section text And that “ASSUME” declaration… You must have an ancient book. That is old, old MASM code. Brings back memories from the early 1980s for me! There are many differences between … Read more
If you look at the various multiplication instructions of x86, looking only at 32bit variants and ignoring BMI2, you will find these: imul r/m32 (32×32->64 signed multiply) imul r32, r/m32 (32×32->32 multiply) * imul r32, r/m32, imm (32×32->32 multiply) * mul r/m32 (32×32->64 unsigned multiply) Notice that only the “widening” multiply has an unsigned counterpart. … Read more
You’re right, a modern x86 will decode add dword [mem], 1 to 3 uops: a load, an ALU add, and a store. (This is actually a simplification of various things, including Intel’s micro-fusion and how AMD always keeps a load+ALU together in some parts of the pipeline…) Those 3 dependent operations can’t happen at the … Read more
An x86 instruction stream is not self-synchronizing, and can only be unambiguously decoded forward. You need to know a valid start-point to decode. The last byte of an immediate can be a 0x90 which decodes as a nop, or in general a 4-byte immediate or displacement can have byte-sequences that are valid instructions, or whatever … Read more
You can’t vpinsrq into a YMM register. Only an xmm destination is available, so it unavoidably zeros the upper lane of the full YMM register. It was introduced with AVX1 as the VEX version of the 128-bit instruction. AVX2 and AVX512 did not upgrade it to YMM/ZMM destinations. I’m guessing they didn’t want to provide … Read more
No, fusion is totally separate from how one complex instruction (like cpuid or lock add [mem], eax) can decode to multiple uops. The way the retirement stage figures out that all the uops for a single instruction have retired, and thus the instruction has retired, has nothing to do with fusion. Macro-fusion decodes cmp/jcc or … Read more