The C++11 memory ordering parameters for atomic operations specify constraints on the ordering. If you do a store with std::memory_order_release, and a load from another thread reads the value with std::memory_order_acquire then subsequent read operations from the second thread will see any values stored to any memory location by the first thread that were prior … Read more
You are thinking in terms of sequential consistency, the strongest (and default) memory order. If this memory order is used, all accesses to atomic variables constitute a total order, and the assertion indeed cannot be triggered. However, in this program, a weaker memory order is used (release stores and acquire loads). This means, by definition … Read more
As of 4.0 (Ice Cream Sandwich), Dalvik’s behavior should match up with JSR-133 (the Java Memory Model). As of 3.0 (Honeycomb), most of the pieces were in place, but some minor things had been overlooked that would be difficult to encounter in practice (e.g. some edge cases in finalization). As of 2.3 (Gingerbread), Dalvik was … Read more
I think Bjarne is wrong about this, or at least, he’s simplifying things considerably. Most modern processors are capable of writing a byte without reading a complete word first, or rather, they behave “as if” this were the case. In particular, if you have a char array[2];, and thread one only accesses array[0] and thread … Read more
Question 1 No. memory_order_relaxed imposes no memory order at all: Relaxed operation: there are no synchronization or ordering constraints, only atomicity is required of this operation. While memory_order_consume imposes memory ordering on data dependent reads (on the current thread) A load operation with this memory order performs a consume operation on the affected memory location: … Read more
The GCC Wiki gives a very thorough and easy to understand explanation with code examples. (excerpt edited, and emphasis added) IMPORTANT: Upon re-reading the below quote copied from the GCC Wiki in the process of adding my own wording to the answer, I noticed that the quote is actually wrong. They got acquire and consume … Read more
Any x86 instruction that has lock prefix has full memory barrier. As shown Abel’s answer, Interlocked* APIs and CompareExchanges use lock-prefixed instruction such as lock cmpxchg. So, it implies memory fence. Yes, Interlocked.CompareExchange uses a memory barrier. Why? Because x86 processors did so. From Intel’s Volume 3A: System Programming Guide Part 1, Section 7.1.2.2: For … Read more
Each thread can be on a different core with its own private registers which Java can use to hold values of variables, unless you force access to coherent shared memory. This means that one thread can write to a value storing in a register, and this value is not visible to another thread for some … Read more