A difference between ARM and the x86 is PIO. There are no special instruction on the ARM to access an I/O device. Everything is done through memory mapped I/O. A second difference is the ARM (and RISC in general) has a separate load/store unit(s) that are separate from normal logic. A third difference is that … Read more
It is worth noting that only external aborts can be configured to be taken in monitor mode, so MMU access faults will not be trapped. As for the main question: the state of all Secure/Non-secure banked registers while in monitor mode is controlled by the state of the cp15 Secure Configuration Register NS bit: when … Read more
Prior to ARMv4, ARM had no native support for loading halfwords and signed bytes. To load a signed byte you had to LDRB then sign extend the value (LSL it up then ASR it back down). This is painful so char is unsigned by default. In ARMv4 instructions were added to handle halfwords and signed … Read more
ARM calls FIQ the fast interrupt, with the implication that IRQ is normal priority. In any real system, there will be many more sources of interrupts than just two devices and there will therefore be some external hardware interrupt controller which allows masking, prioritization etc. of these multiple sources and which drives the interrupt request … Read more
Your bullet points of assumptions all look correct to me, except that you could build a uarch where loads can retire from the OoO core after merely checking permissions (TLB) on a load to make sure it can definitely happen. There could be OoO exec CPUs that do that (update: apparently there are). I think … Read more