You should read carefully some VHDL guide for beginners. I can’t recommend any (maybe someone could?), so I’ll go straight to your mistakes here:
- Never use
std_logic_arith. This libraries are not part of standard, and can be replaced with
- Don’t use
- When you associate one vector to other, they must have equal type and length, as user1155120 and Brian Drummond wrote in comment. In particular, you can’t assign
std_logic_vector(7 downto 0)to
bit_vector(3 downto 0).
There are probably more things done wrong here, but your question is not complete – you didn’t provide any explanation what it should do, no full code, and no testbench.