VHDL Selection machine error in port map

You should read carefully some VHDL guide for beginners. I can’t recommend any (maybe someone could?), so I’ll go straight to your mistakes here:

  1. Never use std_logic_unsigned, std_logic_unsigned, and std_logic_arith. This libraries are not part of standard, and can be replaced with numeric_std.
  2. Don’t use bit or bit_vector type. Use std_logic, and std_logic_vector instead.
  3. When you associate one vector to other, they must have equal type and length, as user1155120 and Brian Drummond wrote in comment. In particular, you can’t assign std_logic_vector(7 downto 0) to bit_vector(3 downto 0).

There are probably more things done wrong here, but your question is not complete – you didn’t provide any explanation what it should do, no full code, and no testbench.

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