How to count pressed keys on FPGA spartan board

The effect you are witnessing is called “bouncing” of the switch. You need to “debounce” the external input. How to synchronize an external input An external input is not synchronous to the internal clock domain. Thus signal edges within the setup or hold time of a register could cause metastability. You need to synchronize your … Read more

shift a std_logic_vector of n bit to right or left

Use the ieee.numeric_std library, and the appropriate vector type for the numbers you are working on (unsigned or signed). Then the operators are `sla`/`sra` for arithmetic shifts (ie fill with sign bit on right shifts and lsb on left shifts) and `sll`/`srl` for logical shifts (ie fill with ‘0’s). You pass a parameter to the … Read more

Is process in VHDL reentrant?

No event will ever occur while a process is running! When a process is woken by an event, it runs to completion (“end process”) or an explicit “wait” statement, and goes to sleep. This takes, notionally, ZERO time. Which means that if you have loops in your process, they are effectively unrolled completely, and when … Read more

VHDL Selection machine error in port map

You should read carefully some VHDL guide for beginners. I can’t recommend any (maybe someone could?), so I’ll go straight to your mistakes here: Never use std_logic_unsigned, std_logic_unsigned, and std_logic_arith. This libraries are not part of standard, and can be replaced with numeric_std. Don’t use bit or bit_vector type. Use std_logic, and std_logic_vector instead. When … Read more