What does “rep; nop;” mean in x86 assembly? Is it the same as the “pause” instruction?

rep; nop is indeed the same as the pause instruction (opcode F390). It might be used for assemblers which don’t support the pause instruction yet. On previous processors, this simply did nothing, just like nop but in two bytes. On new processors which support hyperthreading, it is used as a hint to the processor that … Read more

Why does Java switch on contiguous ints appear to run faster with added cases?

As pointed out by the other answer, because the case values are contiguous (as opposed to sparse), the generated bytecode for your various tests uses a switch table (bytecode instruction tableswitch). However, once the JIT starts its job and compiles the bytecode into assembly, the tableswitch instruction does not always result in an array of … Read more

MARS MIPS simulator’s built-in assembler aligns more than requested?

TL:DR: MARS tooltips are misleading; you need to disable auto-alignment for the rest of the section using .align 0. You can’t just under-align the next word. .align 1 does align by 2, that’s not the problem. e.g. try it between .byte or .ascii pseudo-instructions. e.g. this source produces 0x00110062 as the first word of the … Read more

How does a mutex lock and unlock functions prevents CPU reordering?

The short answer is that the body of the pthread_mutex_lock and pthread_mutex_unlock calls will include the necessary platform-specific memory barriers which will prevent the CPU from moving memory accesses within the critical section outside of it. The instruction flow will move from the calling code into the lock and unlock functions via a call instruction, … Read more

Bomb lab phase_4

edi and esi are the two arguments to func4. This is according to standard calling convention, but can also be deduced from the fact that these registers are used without initialization, so their value must come from outside. As such, the prototype is int func4(int a, int b). Line +23 check to see if a … Read more

Do terms like direct/indirect addressing mode actual exists in the Intel x86 manuals

There aren’t really official names for most forms of x86 addressing modes. They all have the form [base + index*scale + disp8/disp32] (or a subset of any 1 or 2 components of that), except for 64-bit RIP-relative addressing. See Referencing the contents of a memory location. (x86 addressing modes) for a breakdown of what you … Read more

What’s the size of a QWORD on a 64-bit machine?

In x86 terminology/documentation, a “word” is 16 bits because x86 evolved out of 16-bit 8086. Changing the meaning of the term as extensions were added would have just been confusing, because Intel still had to document 16-bit mode and everything, and instruction mnemonics like cwd (sign-extend word to dword) bake the terminology into the ISA. … Read more