How to use all *.c files in a directory with the Cmake build system?
How about the good old globbing? FILE(GLOB MyCSources *.c) ADD_EXECUTABLE(MyExecutable ${MyCSources})
makefile
Difference in details between “make install” and “make altinstall”
Let’s take a look at the generated Makefile! First, the install target: install: altinstall bininstall maninstall It does everything altinstall does, along with bininstall and maninstall Here’s bininstall; it just creates the python and other symbolic links. # Install the interpreter by creating a symlink chain: # $(PYTHON) -> python2 -> python$(VERSION)) # Also create … Read more
How to write loop in a Makefile?
The following will do it if, as I assume by your use of ./a.out, you’re on a UNIX-type platform. for number in 1 2 3 4 ; do \ ./a.out $$number ; \ done Test as follows: target: for number in 1 2 3 4 ; do \ echo $$number ; \ done produces: 1 … Read more
Getting make to create object files in a specific directory
You have two problems in this rule (well, three): $(OBJECTS): $(SOURCES) $(CC) $(CFLAGS) -c $(SOURCES) $(LIB_PATH) $(LIBS) You haven’t noticed yet, but the rule makes each object dependent on all sources, and tries to build that way. Not a problem as long as you have only one source. Easy to fix with a static pattern … Read more
Passing arguments to “make run”
I don’t know a way to do what you want exactly, but a workaround might be: run: ./prog ./prog $(ARGS) Then: make ARGS=”asdf” run # or make run ARGS=”asdf”
Make: how to continue after a command fails?
Try the -i flag (or –ignore-errors). The documentation seems to suggest a more robust way to achieve this, by the way: To ignore errors in a command line, write a – at the beginning of the line’s text (after the initial tab). The – is discarded before the command is passed to the shell for … Read more
How does “make” app know default target to build if no target is specified?
By default, it begins by processing the first target that does not begin with a . aka the default goal; to do that, it may have to process other targets – specifically, ones the first target depends on. The GNU Make Manual covers all this stuff, and is a surprisingly easy and informative read.
GNU Makefile rule generating a few targets from a single source file
The trick is to use a pattern rule with multiple targets. In that case make will assume that both targets are created by a single invocation of the command. all: file-a.out file-b.out file-a%out file-b%out: input.in foo-bin input.in file-a$*out file-b$*out This difference in interpretation between pattern rules and normal rules doesn’t exactly make sense, but it’s … Read more
What do the makefile symbols $@ and $< mean?
$@ is the name of the target being generated, and $< the first prerequisite (usually a source file). You can find a list of all these special variables in the GNU Make manual. For example, consider the following declaration: all: library.cpp main.cpp In this case: $@ evaluates to all $< evaluates to library.cpp $^ evaluates … Read more
What do @, – and + do as prefixes to recipe lines in Make?
They control the behaviour of make for the tagged command lines: @ suppresses the normal ‘echo’ of the command that is executed. – means ignore the exit status of the command that is executed (normally, a non-zero exit status would stop that part of the build). + means ‘execute this command under make -n‘ (or … Read more