Verilog module syntactically might contain declarations, procedural blocks, continuous asisgnments, and module instantiations. The expression like this m[i]=x_aux*h_aux; standing alone confuses the verilog compiler. The fact that it is used inside the ‘generate’ block does not change anything because the latter does not represent such a scope and only in-lines its ins internals.
So, I assume that OP wanted to assign a value to the register ‘m[i]’ (where [i] is a generated index). In verilog this can be done in an procedural block (always block in such a case). So, the correct use, taking in account verilog v2k syntax is:
always @*
m[i]=x_aux*h_aux;
in system verilog I recommend to use this instead:
always_comb
m[i]=x_aux*h_aux;